For the design of a semiconductor integrated circuit, the CAD (Computer Aided Design) technique is usually used. When the logic specification of the semiconductor integrated circuit to be designed is determined, according to this specification, the device design, electronic circuit design, and logic design are carried out in sequence, then, finally, the layout/wiring design is performed. In the layout/wiring design, in accordance with the electronic circuit diagram or logical circuit diagram, the positions for disposing respective functional blocks, such as CPU, memory, and I/O, which are loaded in the chip, are determined by an automatic layout program, then, the wiring routes between these blocks are determined by the automatic wiring program (Router). When the layout/wiring design is completed, based on it, a plotting processing for preparing the mask pattern is conducted.
Referring to FIGS. 11 and 12, a description of a procedure for automatic wiring processing by a conventional router follows. In a chip area 100, the layout positions of a multiple number of functional blocks P1, P2, P3, . . . , Q1, Q2, Q3, . . . are determined in advance by an automatic layout program. In the respective blocks Pi, Qi, signal terminals Ai, Bi (for the convenience of description, 2 types are used) are provided. In the chip area 100, the area other than the blocks P1, P2, P3, . . . , Q1, Q2, Q3, . . . (space area) is the area where the wiring routes can be set, that is, the wiring area. A conventional router typically determines the wiring routes between signal terminals of respective groups in the following manner.
First, the wiring routes for connecting the signal terminals of the first group A1, A2, A3, . . . are determined. For this purpose, for example, the signal terminal A1 of the block P.sub.1 at the left end in the first line is set as the origin. As the positions of the other signal terminals A2, A3, . . . in the first group relative to the said signal terminal A1 can be obtained as vectors, based on those vectors, the partial wiring routes extending along the X-direction or Y-direction are determined in sequence while generating random numbers, by directing those routes towards the other signal terminals A2, A3, . . . , then, by connecting those partial wiring routes, a network-form wiring route WA1 that connects all signal terminals of the first group A1, A2, A3, . . . is obtained (FIG. 11). Next, by executing the foregoing processing again, the other wiring route WA2 is obtained (FIG. 11). Even with the same processing, because the way of appearance of random numbers is different, both wiring routes WA1, WA2 are different at least partially in routes from each other, and they are different also in total distance (total length). In this manner, by repeating the same processing many times, a large number of wiring routes WA1, WA2, WA3, . . . are obtained, then, from these wiring routes, the wiring route that is shortest in total distance WAi is selected (determined) (FIG. 12).
Thereafter, the processing for determining the wiring route for connecting the signal terminals of the second group B1, B2, B3, . . . is executed. Also in this processing, as in the above-mentioned processing, a large number of wiring routes WB1, WB2, WB3, . . . (not shown in the figure) for connecting all connection terminals B.sub.1, B.sub.2, B.sub.3 . . . in the second group are obtained, and, from those wiring routes, the route with shortest distance WBi is selected (FIG. 12).
As mentioned above, in the conventional router, because the method used is that to determine the partial wiring routes in the X-direction or Y-direction in sequence while generating random numbers at places within the wiring area and then to connect them, optional wiring routes which can connect the signal terminals of respective groups A1, A2, A3, . . . , B1, B2, B3, . . . are derived or generated. Among those wiring routes, not only are the simple and clear wiring routes WA1, WA2, WAi, WBi included, as shown in FIGS. 11 and 12, but also many of those which have evidently wasteful or superfluous partial wiring routes, such as that reaching the signal terminal through hunching wa1, that return again after coming out of the channel wiring area once wa2, and that go around the outside of the end block wa3, as shown in FIG. 13. Accordingly, almost infinitely numerous wiring routes WA1, WA2, WA3, . . . , WB1, WB2, WB3, . . . are derived, and the wiring routes WAi, WBi having the shortest total distance are selected from those numerous wiring routes. Consequently, it takes an extremely long time for the processing to be completed. Thus, in actual situations, even in the newest type of workstation, several hours are readily required for processing. Besides, there are many cases in which the wiring routes selected from the large number of derived wiring routes are not the wiring routes shortest in total distance (true shortest distance wiring routes) among all possible wiring routes. As a result, the automatic wiring design has to be done again, or a correction by a manual design has to be carried out.
With such problems in mind, it is an object of the invention to provide an automatic wiring device capable of deriving a shortest distance wiring route efficiently in a short time period in the design of a semiconductor integrated circuit.